1. Field of the Invention
The present invention relates to a logic circuit using a voltage drive type transistor and in particular to a bias circuit used for a system such as LSI.
2. Description of the Related Art
Recent years have witnessed rapid progress in one-chip integration of systems by virtue of complementary metal oxide semiconductors (CMOS) and, associated with this, an increasing demand for a low voltage operating analog circuits. In large scale integration (LSI), it is believed that a digital circuit will operate with a power supply of 1.2 or 1 volts in the future, and this requires that an analog circuit operate on a similar power supply voltage as that of a digital circuit. This brings to the surface the problem caused by the setup of the bias current of a MOS transistor and by variations in the characteristics of MOS transistors in an analog circuit. The variation in the characteristics of the MOS transistors is due to the variation in the fabrication process. Here, the characteristics of the MOS transistors are such as β and Vth.
β is expressed by:β=μCoxW/L, 
where μ, Cox, W and L are the mobility of a MOS transistor, the capacitance of the oxide film of the gate, the gate width and the gate length, respectively. The Vth is the threshold voltage of a MOS transistor.
Here, a description of a bias circuit is provided. The bias circuit is the basis for an analog circuit and is important for assuring stable operation of a circuit. The bias circuit is especially important when designing a high-performance analog circuit and a low-voltage operation circuit.
Analog circuits mainly use a MOS transistor operating on a saturated region. Where the overdrive voltage Vod of the MOS transistor is defined as Vod=Vgs−Vth, a bias voltage is determined so as to make the value of the Vds of the MOS transistor operate in a saturated region in an analog circuit larger than the Vod. Here, the Vth, Vgs and Vds are the threshold voltage, the voltage between the gate and source, and the voltage between the drain and source, of the MOS transistor, respectively.
A CMOS analog circuit is constituted by connecting, between the power supply voltages, a plurality of stages of MOS transistors operating in a saturated region, and therefore the sum of the Vds of the MOS transistor in the individual current paths is equal to the value of the power supply voltage. Therefore, the Vod of the MOS transistor must be set at a progressively smaller level as the power supply voltage is reduced.
Next is a description of the reason. The “upper limit of Vod” of each MOS transistor is determined by the power supply voltage and by the signal amplitude. Accordingly, if the Vod is varied by the fabrication variation, temperature and such, a Vodmax needs to be constrained within the upper limit of the Vod noted above, where the variation range of the Vod is between Vodmin and Vodmax (where the Vodmin is the minimum value of the Vod, and the Vodmax is the maximum value of the Vod). This results inevitably in setting the typical (i.e., on the average) Vod to be smaller than the upper limit of the Vod. The reason is that otherwise the Vodmax exceeds the upper limit of the Vod.
The Vod is determined by the characteristic of a MOS transistor and bias current, where the characteristic of the MOS transistor is varied by the fabrication process. If the bias circuit of the MOS transistor generates a bias current varying the Vod in relation to the variation of the fabrication process, the upper limit of the varying Vod is limited by the power supply voltage as described above, thereby causing the lower limit of the varying Vod to become further smaller in value compared with the limit of the power supply voltage. In the MOS transistor operating on a small Vod, the noise characteristic and matching characteristic are degraded. The degradations of the aforementioned two characteristics are remarkable if there is a need to consider the operation of a MOS transistor on a very small Vod at a low power-supply voltage due to the fabrication process.
Next, a detailed description of the mechanism of degradations of the noise characteristic and matching characteristic of a MOS transistor operating on a small Vod is provided.
Here, the description is provided by exemplifying a current mirror as one of the important analog element circuits.
The drain current Id of a MOS transistor operating in a saturated characteristic zone is given byId=(β/2)Vod2 
using the square-root law, where the β is a constant determined by the fabrication process and temperature and by the size of the transistor.
In this case, parameter gm (i.e., mutual inductance) indicating a change in current relative to a change in the voltage of the MOS transistor in given bygm=dId/dVod=βVod 
This results in:gm=2Id/Vod 
The above expression makes it comprehensible that the amount gm of the change in current relative to the Vod is inversely proportional to the Vod under the condition of a certain bias current Id. Further, since Vod=Vgs−Vth, the Vod is varied by noise (i.e., flicker noise or/and external noise) overlapped on the Vgs and by the error in Vth (i.e., the variation in Vths of the fabricated individual MOS transistors). The ratio of the variation of the Vod to the error in current can be defined as the gm, and therefore the larger the gm under the condition of a certain bias current Id becomes, the greater the influence of the error in noise and matching. Therefore, the smaller the Vod inversely proportional to the value of gm becomes, the more the noise characteristic and matching characteristic degrade.
A bias circuit compensating the variations of bias current and the variations of the gm of a transistor and maintaining it against the variations of the fabrication process has conventionally been invented. A bias circuit compensating for the variation in Vod of a transistor relative to the fabrication process variation of the transistor, however, has not been invented.